The present invention is related to semiconductor devices and methods of forming the same, and more particularly, to resistive semiconductor devices and methods of forming the same.
A semiconductor memory device may be classified as a volatile memory device or a non-volatile memory device, depending on whether or not a power supply is required for retaining the stored data in memory. A volatile memory device, such as a DRAM or an SRAM may have a rapid processing speed, but may be limited, in that a volatile memory device may require a power supply in order to save data. A non-volatile memory device, such as a phase-change memory device (PRAM), resistive memory device (RRAM), ferroelectrics memory device (FRAM), etc., may not require a power supply to retain data.
A resistive memory device (RRAM) may include one or more variable resistive oxide layers. The resistance of a variable resistive oxide layer varies in response to a program voltage supplied to an upper electrode and/or a lower electrode on opposite sides of the variable resistive oxide layer. The specific resistance of the variable resistive oxide layer may vary by up to more than 100 times, depending on the amplitude of the program voltage. The specific resistance of the variable resistive oxide layer may be maintained even when a power supply voltage is not supplied. In order to read data stored in an RRAM cell, voltage variance and/or current flow variance through a variable resistive oxide layer may be detected based on the difference in specific resistance of the variable resistive oxide layer. Thus, it can be determined whether the data recorded on the variable resistive oxide layer represents a logic “1” or a logic “0”.
When a variable resistive oxide layer is switched from a high resistance state to a low resistance state, a large amount of current may flow in the device. This may result in breakdown of insulation of the variable resistive oxide layer, and the reliability of the resistive memory device may be impaired.